High speed communication devices require phase lock loops (PLLs) with fast lock times. For example, when operating according to a wireless cellular protocol such as iDEN (integrated digitally enhanced network), the PLL lock time should be on the order of two milliseconds (msec). A PLL typically exhibits an inverse relationship to the closed loop bandwidth of the PLL. Accordingly, to achieve a short PLL lock time, the PLL needs to have a wide loop bandwidth. In addition to the fast lock time specification, the high speed communication devices also have demanding sideband noise requirements to reduce adjacent channel interference. For example, sideband noise in the iDEN wireless cellular protocol cannot be more than 117 decibels (dB) at 25 KiloHertz (KHz) offset from the carrier frequency. Undesired noise generated from a phase detector or a charge pump in the PLL increase the sideband noise. To reduce the sideband noise, the PLL loop bandwidth may be reduced. However, reducing the loop bandwidth of a PLL increases the lock time of the PLL. Therefore, using a larger loop bandwidth in a PLL decreases the lock time of the PLL at the expense of increasing the sideband noise of the PLL. Similarly, using a smaller loop bandwidth in a PLL decreases the sideband noise of the PLL at the expense of increasing the lock time of the PLL. Accordingly, a tradeoff exists between the lock time and the phase noise performance of a PLL.
One solution to avoid this tradeoff uses a first PLL with a large bandwidth and a second PLL with a small bandwidth. However, the use of two PLLs is expensive compared to using a single PLL. Another solution uses a single PLL that uses different loop filters at different times to produce different loop bandwidths are different times. However, switching from one loop filter to another causes an undesirable frequency glitch in the PLL output. Yet another solution uses a single PLL that uses a single loop filter, but changes the resistance value of a variable resistor in the loop filter to produce different loop bandwidths. However changing the resistance value of the variable resistor also causes an undesirable frequency glitch in the PLL output.
Accordingly, a need exists for a PLL and method of operation that reduces the lock time of the PLL when switching from one frequency to another. It is also desirable for he PLL and method of operation to minimize the phase noise in the output signal of the PLL and to minimize frequency glitches in the output signal of the PLL.